Dynamic Random Access Memory (DRAM) employs capacitors of its memory cells to reserve charges by external power supply. As a result of the improvement of Very Large Scale Integrated circuits (VLSI) technology, the memory density is moving toward a higher capacity, thus multiplying the number of memory cells. Those multiplied memory cells consume a great amount of power supply, but the power specification of the printed circuit board, on which the DRAM is mounted, has remained the same or has even been reduced over the past decades. Therefore, while the number of memory cells and memory density have greatly increased, the internal power consumption has become a vital issue for DRAMs.
For overcoming the disadvantage of high power consumption of the DRAM, a traditional power down scheme is employed to turn off a regulator to cut off internal power supply of the DRAM for saving, on power consumption. When the DRAM enters the power down state, a power down signal responsive to a clock enable signal, which would suspend an internal clock of DRAM, turns off the regulator, thereby stopping the internal power supply for the peripheral circuits and memory banks of the DRAM.
In designing the power down scheme, it is important to carefully consider the relation between the clock enabling signal and ACT command, which is employed to turn on the gates along a selected word line. Since the ACT command takes a period to completely turn on the gates of selected word line, when the clock enable signal follows the ACT command immediately, it would suspend the internal clock, thereby risking the information read or written by the ACT command under incompletion.
In addition, the control of self-refresh clock is also an important concern whiling designing the power down scheme. The self-refresh clock is a normally stable signal. When the self-refresh clock enters the self-refresh mode, it would toggle at a specific frequency to inform the control circuit of the DRAM to refresh its memory cells. Meanwhile, the internal power supply is not available to be cut off due to the proceeding refresh mode. Since the power down scheme could only be activated under a non-refresh mode, correctly detecting the self-refresh clock's waveform for making sure the refresh state turns out to be a key issue for designing power schemes.
As illustrated above, only if the ACT command is completed and the non-refresh mode is detected, the power down scheme would turn off the regulator to decrease the power consumption of the DRAM. Under this understanding, this power down system is proposed to meet the above criteria to save power consumption of the DRAM.